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VLSI Course Details

VLSI



Advanced Digital Design 40 Hours

System Architecture 36 Hours

Linux Shell Scripting & Perl 60 Hours

Programming Fundamentals for Design and Verification 70 Hours

Verilog HDL 120 Hours

HDL Simulation and Synthesis 110 Hours

CMOS VLSI and Aspects of ASIC Design 74 Hours

SystemVerilog 90 Hours

Verification using UVM 80 Hours

Effective Communication 50 Hours

Aptitude & General English 50 Hours

Project 120 Hours


Fees

The total fees of the course is Rs. 90,000/- plus Goods and Service Tax (GST) currently 18%.

The course fees has to be paid in two installment as per the schedule.

First installment is Rs. 10,000/- plus Goods and Service Tax (GST) currently 18%.

Second installment is Rs. 80,000/- plus Goods and Service Tax (GST) currently 18%.

Placement

Overall placement for VLSI course is very normal dont expect too much calls like DAC

No of interview calls are depends on your ccee exam score.

CCEE

Colleges For VLSI :

1. CDAC ACTS Pune

2. CDAC Hyderabad

Job Profile In VLSI

Perl Developer

Linux Administrator

VLSI Designer

PG-DVLSI is a pioneering course offered by C-DAC to assist engineers who wish to gain theoretical as well as practical knowledge in the field of Very Large Scale Integration (VLSI) design. It will also prepare them to keep pace with the changing trends of VLSI technology and the requirements of an ever-growing VLSI design industry. The entire course syllabus, courseware, teaching methodology and the course delivery have been derived from the rich research and development background of C-DAC, which has a legacy of designing the PARAM range of supercomputers.

Centers for VLSI

1. CDAC ACTS Pune

2. CDAC Hyderabad

After Course Complete :

After completion of course students will be able to develop field-programmable gate array (FPGA) implementations, application-specific integrated circuit (ASIC) designs, CMOS design and SoCs in VLSI industry as VLSI designer/ chip designer. Students will also be able to develop a programmable chip using verilog and system verilog languages..

DITTIS Eligibility:



Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR MSc/MS (10+2+3+2 years) in Computer Science, IT, Electronics.

Mathematics in 10+2 (exempted for candidates with Diploma + Engineering) OR

Post Graduate in Mathematics or allied areas, OR

MCA

The candidates must have secured a minimum of 55% marks in their qualifying examination.




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